As cell dimensions in memory devices scale to smaller dimensions, the integrity of data storage is challenged. In particular, the raw bit error rate in non-volatile memory devices such as NAND flash memory has been observed to increase with decreasing cell size. NAND technology relies on an error correction code (ECC) process to compensate for bits that may spontaneously fail during normal device operation.
In order to achieve a tolerable bit error rate, an error correction engine is typically employed at the system level. The most common ECC that has been employed in recent generations of NAND products uses a so-called BCH code (the acronym is derived from the inventor's names Bose, Ray-Chaudhuri, and Hocquenghem). However, BCH code may not be able to deliver the error correction capability that may be required in future generation NAND products where the cell size is smaller.
On the other hand, error codes such as the low density parity check (LDPC) provide greater capability but require that a NAND memory provide data in a different manner than conventional user data. Unlike the BCH method, LDPC code involves providing, in addition to each bit value, so-called state confidence data, which is data that provides an estimate of the bit's reliability. LDPC can yield significant correction capability gains over BCH, because the decoder is able to determine which bits are more likely to be flipped and can use this information in its correction algorithms. However, efficient methods for generating state confidence data from a memory without unduly affecting performance are lacking.
Accordingly, there may be a need for improved techniques and apparatus to solve these and other problems.